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M64897GP
PLL Frequency Synthesizer with DC/DC Converter for PC
REJ03F0167-0200 Rev.2.00 Jun 14, 2006
Description
The M64897GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR/PC using I2C BUS control. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and DC/DC converter for Tuning voltage.
Features
* * * * * * * * Built-in DC/DC converter for Tuning voltage 4 integrated PNP band drivers (IO = 30 mA, Vsat = 0.2 V Typ.@VCC1 to 10 V) Built-in prescaler with input amplifier (f max = 1.3 GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X'tal 4 MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64894 Built-in Power on reset system Small Package (SSOP)
Application
PC, TV, VCR tuners
Recommended Operating Condition
* Supply voltage range VCC1 = 4.5 to 5.5 V VCC2 = VCC1 to 10 V * Rated supply voltage VCC1 = 5 V VCC2 = VCC1
Rev.2.00 Jun 14, 2006 page 1 of 13
M64897GP
Block Diagram
VCC1 3
VDC 9
Ipk 10
SQ
Xin 20
OSC
fREF Divider
Selector
2
DIV.
R
11 SWE
Latch
fin 1
AMP
1/8
-
Latch
15
+
Vreg
12 +B
1/32, 1/33
15-bit Programmable Divider
Phase Detector
Charge Pump
CP TEST
13 Vtu
OS
14 Vin
SCL 17
SDA 18
ADS 19
Bias/Band Switch Driver
1
Bus Controller Address Select
Lock Detector
5
3
Latch
4
1
5-level ADC
16 LD/ftest
Power-on Reset
4 VCC2
5 BS4
6 BS3
7 BS2
8 BS1
2 GND
15 ADC
Rev.2.00 Jun 14, 2006 page 2 of 13
M64897GP
Pin Arrangement
M64897GP fin GND VCC1 VCC2 BS4 BS3 BS2
BS1 VDC
1
20 Xin 19 ADS 18 SDA 17 SCL 16 LD/ftest 15 ADC 14 Vin
13 Vtu
2 3 4 5 6 7
8 9
12 +B 11 SWE
Ipk 10 (Top view)
Outline: PLSP0020JA-A (20P2E-A)
Rev.2.00 Jun 14, 2006 page 3 of 13
M64897GP
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC Ipk Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V. Power supply voltage terminal.5.0 V 0.5 V Power supply for band switching, VCC1 to 10 V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. DC/DC power supply voltage terminal.5.0 V 0.5 V When potential difference with VDC terminal becomes more than 0.33 V by current limiting detector of DC/DC converter, the listing rises with off. DC/DC converter oscillator output. Power supply voltage for tuning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fREF), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. In control byte data input, the programmable freq. divider output and reference freq. output is selected by the test mode. A/D conversion of the input voltage. Data is read into the shift register when the clock signal falls.. Input for band SW and programmable freq. divider set up. In lead mode, it outputs lock detector output and power down flag and a state of 5 level A/D converter. Chip address sets it up with the input condition of terminal. 4.0 MHz crystal oscillator is connected.
DC/DC power supply voltage Peak current detect
11 12 13 14
SWE +B Vtu Vin
Switching output Power supply voltage Tuning output Filter input (Charge pump output)
15
LD/ftest
Lock detect/Test port
16 17 18
ADC SCL SDA
AD converter input Clock input Data input
19 20
ADS Xin
Address switching input This is connected to the crystal oscillator
Rev.2.00 Jun 14, 2006 page 4 of 13
M64897GP
Absolute Maximum Ratings
(Ta = -20C to +75C, unless otherwise noted)
Item Supply Voltage 1 Supply voltage 2 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Symbol VCC1 VCC2 VI VO VBSOFF IBSON tBSON Ratings 6.0 10.8 6.0 6.0 10.8 40.0 10 Unit V V V V V mA s Condition Pin 3 Pin 4 Not to exceed VCC1 fREF output
Per 1 band output circuit 40 mA per 1 band output circuit 3 circuits are pn at same time. Ta = 75C
Pd Topr Tstg
255 -20 to +75 -40 to +125
mW C C
Recommended Operating Conditions
(Ta = -20C to +75C, unless otherwise noted)
Item Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol VCC1 VCC2 fopr1 fopr2 IBDL Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA Conditions Pin 3 Pin 4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time.
Rev.2.00 Jun 14, 2006 page 5 of 13
M64897GP
Electrical Characteristics
(Ta = -20C to +75C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V)
Item Input termina ls "H" input voltage "L" input voltage "H" input current "L" input current "L" output voltage Leak current "H" output voltage "L" output voltage Output voltage Leak current Symbol VIH VIL IIH IIL VOL ILO VOH VOL VBS Iolk1 Test Pin 17 to 18 17 to 18 17 to 18 17, 18 18 18 16 16 5 to 8 5 to 8 Min. 3.0 -- -- -- -- -- 5.0 -- 11.6 -- Limits Typ. -- -- -- -4/-14 -- -- -- 0.3 11.8 -- Max. VCC1 + 0.3 1.5 10 -10/-30 0.4 10 -- 0.5 -- -10 Unit V V A A A A V V V A Test Conditions
SDA output Lock output Band SW
VCC1 = 5.5V, Vi = 4.0V VCC1 = 5.5V, Vi = 0.4V VCC1 = 5.5V, IC = 3mA VCC1 = 5.5V, VO = 5.5V VCC1 = 5.5V VCC1 = 5.5V VCC2 = 9V, IO = -30mA VCC2 = 9V, Band SW is OFF VO = 0V +B = 31V +B = 31V VCC1 = 5.0V, VO = 2.5V VCC1 = 5.0V, VO = 2.5V VCC1 = 5.5V VCC2 = 9V VCC2 = 9V VCC2 = 9V, IO = -30mA
Tuning output
Output voltage "H" Output voltage "L"
VtoH VtoL ICPO ICPLK ICC1 ICC2A ICC2B
13 13 14 14 3 4 4
30.5 -- -- -- -- -- --
-- 0.2 270 -- 20 -- 4.0
-- 0.4 370 50 30 0.3 6.0 36.0
V V A nA mA mA mA mA
Charge pump
"H" output current Leakage current Supply current 1 4 circuits OFF Supply current 1 circuits ON, 2 Output open
4 -- 34.0 Output current 30 ICC2C mA DC/DC Converter Supply current (action) ICCdc 9 -- 1.3 Output voltage Vdo 12 28 31 OSC frequency fOSC 11 -- 571 Current limit detect voltage Vipk 10 -- 330 Note: The typical values are at VCC1 = 5.0 V, VCC2 = 9.0 V, Ta = +25C.
3.0 35 -- --
mA V kHz mV
VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V
Rev.2.00 Jun 14, 2006 page 6 of 13
M64897GP
Switching Characteristics
(Ta = -20C to +75C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V)
Item Prescaler operating frequency Operation input voltage Symbol fopr Vin Test Pin 1 1 Min. 80 -24 -27 -15 0 4.7 4 4.7 4 4.7 0 250 -- -- 4 Limits Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1300 4 4 4 100 -- -- -- -- -- -- -- 1000 300 -- Unit MHz dBm Test Conditions VCC1 = 4.5 to 5.5V Vin = Vinmin to Vinmax VCC1 = 4.5 to 5.5V 850 to 100MHz 100 to 950MHz
Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time
fSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO
17 18 17 17 17 17, 18 17, 18 17, 18 17, 18 17, 18 17, 18
kHz s s s s s s ns ns ns s
950 to 1300MHz VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V
Rev.2.00 Jun 14, 2006 page 7 of 13
M64897GP
Method of Setting Data
The input information to consist of 2 or data of 4 bytes to lead to chip address is received in I2C bus receiver. It shows a definition of bus protocol admitted in the following. 1_STA CA CB 2_STA CA D1 3_STA CA CB 4_STA CA D1 STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : Band SW data byte D1 : Divider data byte D2 : Divider data byte BB D2 BB D2 STO STO D1 CB
D2 BB
STO STO
The information of 5 bytes necessary for circuit operation is chip address and control data, band SW data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and "0" goes ahead of divider data, and "1" goes ahead of control data, band SW data.
SDA
SCL S STA
1-7 Address CA
8 0
9 ACK
1-7 Data
8
9 ACK
1-7 Data
8
9
ACK
P STO
Write Mode Format
Byte Address byte Divider byte 1 Divider byte 2 Control byte 1 Band SW byte MSB 1 0 N7 1 X
1 N14 N6 X X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 BS4 MA1 N10 N2 RSa BS3 MA0 N9 N1 RSb BS2 0 N8 N0 OS BS1
LSB A A A A A
Read Mode Format
Byte
Address byte Status byte 1
MSB 1 POR
1 FL
0 X
0 X
0 X
MA1 A2
MA0 A1
1 A0
LSB A A
Rev.2.00 Jun 14, 2006 page 8 of 13
M64897GP
Data Cording Example
Write Mode Format Example
Byte Address byte Divider byte 1 Divider byte 2 Control byte 1 Band SW byte MSB 1 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 LSB 1 1 1 1 1 Condotion in Data Setting ADS input VCC1 Divider ratio N = 16544 fREF divider ratio 1/1024 BS4 output ON
Note: fVCO = N * 8 * fREF = 16544 * 8 * (4 MHz/1024) = 517 MHz
Read Mode Format Example (Loop locked)
Byte Address byte Status byte MSB 1 0 1 1 0 1 0 1 0 1 1 0 1 1 1 1 LSB 1 1 Condotion in Data Setting ADS Applied voltage 0.9 VCC1 to VCC1 ADS Applied voltage 0.45 VCC1 to 0.6 VCC1
Use data input for "1" so that the data of Read mode and Write mode return ACK signal "0" to micro computer in 9 bits of each byte.
Test Mode Data Set Up Method
Test Mode Bit Set Up X MA1, MA0 : Random, 0 or 1. normal "0" : Programmable address bit
MA0 0 1 0 1
Address Input Voltage MA1 0 to 0.1 VCC1 0 Always valid 0 0.4 VCC1 to 0.6 VCC1 1 0.9 VCC1 to VCC1 1 Note: N14 to N0: How to set dividing ratio of the programmable the divider Dividing ratio = N14 (214 = 16384) + +N0 (20 = 1)
Therefore, the range of divider N is 1,024 to 32,768 Example) fVCO
= fREF * 8 * N
= 3.90625 * 8 * N = 31.25 * N (kHz)
T2, T1, T0: Setting Up for The Test Mode
T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge Pump Normal operation High impedance Sink Source High impedance High impedance Pin 12 Condition ADC input ADC input ADC input ADC input fREF output f1/N output Mode Normal operation Test mode Test mode Test mode Test mode Test mode
Rev.2.00 Jun 14, 2006 page 9 of 13
M64897GP RSa, RSb: Set Up for The Reference Frequency Divider Ratio
RSa 1 0 X RSb 1 1 0 Divider Ratio 1/512 1/1024 1/640
OS: Set Up The Tuning Amplifier
OS 0 1 Tuning Voltage Output ON OFF Mode Normal Test
POR : Power on reset flag. "1" output at reset FL : Lock detector flag. "1" output at locked, "0"output at unlocked A2, A1, A0: 5 Level A/D Converter Output Data
ADC Input Voltage 0.6 VCC1 to VCC1 0.45 VCC1 to 0.6 VCC1 0.3 VCC1 to 0.45 VCC1 0.15 VCC1 to 0.3 VCC1 0 to 0.15 VCC1 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0
Note: The voltage accuracy allowance range: 0.03 VCC1 (V)
Power on Reset Operation
(Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency division ratio Lock detect : OFF : High impedance : OFF : 270 A : 1/1024 :H
Charge pump current is replaced by 70 A when locks it by automatic change facility.
Rev.2.00 Jun 14, 2006 page 10 of 13
M64897GP
Timing Diagram
Start condition SDA
tLOW tR tF tHDSTA
tBUF
SCL
tSUSTO
tHDSTA
tHDDAT
tHIGH
tSUDAT
tSUSTA
Stop condition
Start condition
Stop condition
Crystal Oscillator Connection Diagram
20 18 pF 4 MHz
Crystal oscillator characteristics Actual resistance: less than 300 Load capacitance: 20 pF
Rev.2.00 Jun 14, 2006 page 11 of 13
M64897GP
Application Example
Built-in PLL Tuner IF AGC
IF
AGC
VHF UHF 4-Band Tuner
AFT
+B
BS4
BS3
BS2
BS1
Lo
VT
33 H 0.01
+
0.1 100 p 43
56 k 1000 p 1500 p 56 k 0.1 14
VCC1 to 9 V 22 k 68 H 13 9 10 11
M64897GP
4
5
6
7
8
1 AMP
Bias Circuit
Band Driver 4
1/8 1/32 1/33 Charge Pump Phase Detector
+
Q S
R
Power-on Reset
-
3 +5 V Main Counter 10
Vreg
OSC Divider
12 1.5 2 18 p 20 15 4 MHz
Swallow Counter
I C Receiver 5
2
Lock Detector
51 k
Chip Select
+
VCC1 =5V 17 18
5-level ADC
18
19 VCC1
1000 p
ADS MCU
SCL
SDA
LD/ftest
Units R: C: F
Note: Filter constant is for reference. Add a capacitor to stabilize the filter circuit.
Rev.2.00 Jun 14, 2006 page 12 of 13
M64897GP
Package Dimensions
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JA-A Previous Code 20P2E-A MASS[Typ.] 0.08g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2 A1
*2
D
Reference Dimension in Millimeters Symbol
*3
e
bp
Detail F
y
D E A2 A A1 bp c HE e y L
Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7
Min 6.4 4.3
Rev.2.00 Jun 14, 2006 page 13 of 13
A
L
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